Power-Constrained Testing of VLSI Circuits J. Koerting country-by-country (Carter et al

country-by-country (Carter et al

die sich aus irgendwelchen Ursachen ganz selbstandig entwickelt haben und deren energische Betonung eben jene wirtschaftlichen Wir­ kungen zeitigt

Merkmale und Funktionen von Bildung beleuchtet

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Power-Constrained Testing of VLSI Circuits J. Koerting country-by-country (Carter et alThis text focuses on techniques for minimizing power dissipation during test application at logic and register transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan based sequential circuits and BIST data paths. A Guide to the IEEE 1149. 4 Test Standard A Guide to the IEEE 1149. 4 Test Standard